Stanford's Hazy Research group recently explored how to maximize the speed of open-source models on modern GPUs, particularly in the challenging scenario of generating a single sequence with Llama-3.2-1B. Their findings reveal significant performance limitations in popular LLM inference engines and introduce a "megakernel" approach that delivers better speed improvements comparing to other approaches.
They identified an opportunity when running a single sequence with Llama-1B, performance is strongly memory-bound, meaning that execution speed is primarily limited by how quickly model weights can be loaded from GPU global memory. Popular LLM inference engines like vLLM and SGLang are only able to utilize at most 50% of the available GPU bandwidth when running this workload on high-performance accelerators like NVIDIA's H100.
The core problem is that existing systems break down a model's forward pass into approximately one hundred separate kernels, each implementing only a few operations such as RMS normalization, attention mechanisms, MLP layers with activations, and rotary position embeddings. Each of these kernels comes with setup and teardown periods during which no useful work is performed and creates overhead, resulting in inefficiencies.
Three key problems with the current kernel-based approach that create what they call "memory pipeline bubbles"—periods when the GPU is not actively loading from memory:
Strict Ordering of GPU Kernels: GPU kernels are launched in a strict sequence where thread blocks in a new kernel cannot start until all thread blocks from previous kernels have completely finished. This creates waiting periods as stragglers finish their work.
Kernel Launch and Teardown Costs: Each kernel launch incurs overhead. Even with NVIDIA's CUDA graphs (designed to hide these costs), measurements on an H100 showed launch costs of about 1.3 microseconds per kernel—time during which the GPU performs no useful work.
Weight and Activation Loading Delays: After a new kernel starts, the GPU must wait to load weights and activations before computation can begin. These latencies result in thousands of idle cycles.
For a model like Llama-1B with 16 layers and approximately 7 kernel launches per layer, even with an optimistic 5 microseconds of stalling per kernel, these inefficiencies limit performance. The theoretical memory limit on an H100 would allow approximately 1,350 forward passes per second, but pipeline bubbles reduce this to around 770 forward passes per second or even lower with further inefficiencies.
To address these limitations, one approach could be to merging the entire Llama-1B forward pass into a single "megakernel" that eliminates kernel boundaries altogether. This approach achieves remarkable performance, utilizing 78% of memory bandwidth on an H100 and outperforming existing systems by over 1.5x.
However, there are many challenges building and pipelining all of the kernel operations into a single kernel.
Challenge 1: Fusing Numerous Operations
Traditional kernel fusion typically merges just two or three operations, but the Llama-1B forward pass requires fusing approximately one hundred operations. To manage this complexity, one needs to build an on-GPU interpreter where each streaming multiprocessor (SM) receives and executes a sequence of instructions. In order to do so, there are several key instructions for their Llama forward pass megakernel:
Fused RMS norm & QKV & RoPE instruction
Attention computation instruction
Attention reduction instruction (for ThunderGQA on long sequences)
O-projection + residual instruction
Fused RMS norm & up-gate & SiLU instruction
Down-projection + residual instruction
RMS norm & language modeling head instruction
These instructions were implemented using a common CUDA template with standardized load, store, and compute functions to ensure interoperability within the interpreter framework.
Challenge 2: Managing Shared Memory Resources
The megakernel architecture allows for pipelining memory loads across instructions, starting to load weights for an upcoming instruction even while a previous instruction is still finishing. However, this creates a resource allocation challenge: the loaded weights need somewhere to be stored.
The solution was to implement a shared memory paging system. On an H100, the authors of the blog post divided the first 213KB of shared memory into thirteen 16KB pages, with remaining shared memory reserved for instruction parameters. Instructions explicitly request and release these pages from the interpreter, which automatically passes released pages to subsequent instructions. This allows new instructions to begin loading data as soon as shared memory becomes available, which also helps increasing utilization of the memory bandwidth.
Challenge 3: Explicit Synchronization
In traditional multi-kernel execution, CUDA ensures that all input tensors for a kernel are fully produced and available before the kernel launches. With megakernels, this guarantee doesn't exist—when an SM starts executing a new instruction, its inputs might not be ready.
To address this synchronization challenge, the authors implemented a counter system in GPU global memory. When an instruction completes, it increments a specific counter; when a new instruction starts, it waits for relevant counters to reach target values, confirming that all dependencies have been satisfied.
This approach enabled advanced optimizations like chunking the intermediate state in multi-layer perceptrons (MLPs). Rather than waiting for the entire hidden state to complete before beginning the down projection matrix multiply (as would be necessary with PDL), the megakernel produces and consumes the intermediate state in four chunks, each with its own counter. This allows the down projection to start processing a chunk as soon as it's ready, without waiting for the entire hidden state.
Performance Results
The megakernel approach improved the existing implementation through speed quite a bit:
On an H100, it runs almost 2.5x faster than vLLM and over 1.5x faster than SGLang.
On a B200, the performance gap with vLLM increases to over 3.5x, while maintaining more than 1.5x advantage over SGLang.
Other Approaches
While the megakernel approach demonstrates superior performance, the authors also acknowledge other technical approaches have their own merits:
CUDA Graphs: This NVIDIA feature helps hide kernel launch costs, reducing launch overhead from about 2.1 microseconds to 1.3 microseconds on an H100. While this represents a 38% improvement, it still leaves significant performance on the table compared to the megakernel approach.
Programmatic Dependent Launch (PDL): This NVIDIA mechanism allows the next kernel to start preparing while the previous kernel is running, potentially improving pipelining.However, the authors found that PDL's synchronization mechanism (cudaGridDependencySynchronize) is too coarse-grained. For example, it requires waiting for all queries, keys, and values to complete before starting attention calculations, rather than allowing heads to start as soon as they're ready. The megakernel's fine-grained counter-based synchronization offers more flexibility and efficiency.
Traditional Kernel-Based Execution: The standard approach of dividing operations into separate kernels does provide automatic synchronization guarantees and simpler programming models. However, these benefits come at the cost of significant performance penalties for low-latency, memory-bound workloads.
Libraries
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or msf
/ Metasploit Framework, garak does somewhat similar things to them, but for LLMs.
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garak's a free tool. We love developing it and are always interested in adding functionality to support applications.
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Below the Fold
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Traditional todo apps can be overwhelming.
Ephe is designed to organize your tasks with plain Markdown.
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Some of its key features are:
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